HPC Usability Research Team

The mission of the HPC Usability Research Team is to research and develop a framework for liberating large-scale HPC (high-performance computing) for end-users and developers.

In order to achieve our mission, we conduct research in the following three topics:

Computing Portal Framework

Computing portal that lowers the threshold for using, providing, and aggregating computing/data services

Virtualization Technologies

Virtualization technologies for achieving security and fairness among services, users, and providers. In addition, we also study lightweight virtualization techniques for realizing virtual large-scale HPC for test, debug, and verification of services.

Program Analysis/Verification

Software verification approaches for large-scale parallel programs on the basis of static/dynamic analysis of deterministic parallelism.

Toshiyuki Maeda (Team Leader)
Masatomo Hashimoto (Researcher)
Peter Bryzgalov (Researcher)
Itaru Kitayama (Techinical Staff)

External Collaborators

Tatsuya Abe (Visiting Researcher: CIT STAIR)
Yoshiki Nishikawa (Visiting Researcher: University of Tokyo)
Yves Caniou (Visiting Researcher: University of Tokyo)
Judit Gimenez (Visiting Researcher: Barcelona Supercomputing Center)
Sameer Shende (Visiting Researcher: University of Oregon)
Fabien Delalondre (Visiting Researcher: École polytechnique fédérale de Lausanne)
Pramod Kumbhar (Visiting Researcher: École polytechnique fédérale de Lausanne)
Brian Wylie (Jülich Supercomputing Centre)

Refereed Papers

Shimazaki, T., Hashimoto, M., and Maeda, T.:
"Developing a High Performance Quantum Chemistry Program with a Dynamic Scripting Language"
In Proceedings of the 3rd International Workshop on Software Engineering for High Performance Computing in Computational Science and Engineering (SEHPCCSE15), online. (2015)
Kitayama, I., Wylie, B. J. N, and Maeda, T.:
"Execution Performance Analysis of the ABySS Genome Sequence Assembler using Scalasca on the K computer"
In Proceedings of ParCo2015. (2015)
Abe, T. and Maeda, T.:
"Towards a Unified Verification Theory for Various Memory Consistency Models"
In Proceedings of the 6th Workshop on Syntax and Semantics of Low-Level Languages (LOLA 2015), Short Paper, online. (2015)
Hashimoto, M., Terai, M., Maeda, T., and Minami, K.:
"Extracting Facts from Performance Tuning History of Scientific Applications for Predicting Effective Optimization Patterns"
In Proceedings of the 12th Working Conference on Mining Software Repositories (MSR 2015). (2015)
Hashimoto, M., Mori, A., and Izumida, T.:
"A Comprehensive and Scalable Method for Analyzing Fine-grained Source Code Change Patterns"
In Proceedings of the International Conference on Software Analysis, Evolution, and Reengineering (SANER 2015), pp. 351-360. (2015)
Abe, T. and Maeda, T.:
"Optimization of a General Model Checking Framework for Various Memory Consistency Models"
In Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models (PGAS 2014), pp. 14:1-14:10. (2014)
Terai, M., Bryzgalov, P., Maeda, T., and Minami, K.:
"Extending Kscope Fortran Source Code Analyzer with Visualization of Peformance Profiling Data and Remote Parsing of Source Code"
In Proceedings of the 6th International Symposium on Advances of High Performance Computing and Networking (AHPCN) within Inrternational Conference on High Performance Computing and Communications (HPCC-2014), pp. 878-885. (2014)
Abe, T. and Maeda, T.:
"A General Model Checking Framework for Various Memory Consistency Models"
In Proceedings of the 19th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2014). (2014)
Abe, T. and Maeda, T.:
"Model Checking with User-Definable Memory Consistency Models"
In Proceedings of the 7th Conference on Partitioned Global Address Space Programming Models (PGAS 2013), Short paper, online. (2013)
Abe, T., Maeda, T., and Sato, M.:
"Model Checking Stencil Computations Written in a Partitioned Global Address Space Language"
In Proceedings of the 18th International Workshop on High-Level Parallel Programming Models and Supportive Environments (HIPS 2013). (2013)
Abe, T., Maeda, T., and Sato, M.:
"Model Checking with User-Definable Abstraction for Partitioned Global Address Space Languages"
In Proceedings of the 6th Conference on Partitioned Global Address Space Programming Models (PGAS 2012), online. (2012)

Non-Refereed Papers

Hashimoto, M. and Maeda, T.:
"Toward Evidence-Based Performance Tuning Assistant"
The 20th Annual Conference of the Japan Society for Computational Engineering and Science (JSCES 2015). (2015) (in Japanese)

Invited Talks

Hashimoto, M.:
"Towards Evidence-based Performance Tuning Assist"
The 6th Symposium on Automatic Tuning Technology and its Application (ATTA 2014). (2014) (in Japanese)

Presentations

Abe, T.:
"Compositional Concurrent Program Logic for Relaxed Memory Consistency Models"
Workshop on Computer Science and Category Theory (CSCAT 2015). (2015) (in Japanese)
Kitayama, I.:
"Parallel File I/O Optimization with SIONlib"
Japan Lustre Users Group 2014 (JLUG 2014). (2014)
Hashimoto, M.:
"Constructing Finge-Grained Tuning Cases Database and Its Application for Prediction of Effective Program Optimizations"
The 10th Autotuning Research Group’s Open Academic Session (ATOS10). (2014) (In Japanese)
Abe, T.:
"Towards Semi-automatic Theorem Proving Considering Memory Consistency Models"
The 25th Algebra, Logic, Geometry and Informatics (ALGI). (2014) (In Japanese)
Abe, T.:
"Program Verification for Formalized Relaxed Memory Consistency Models"
The 31st Symbolic Logic and Computer Science (SLACS). (2014) (In Japanese)
Kitayama, I.:
"A User's Experience with FEFS"
In Japan Lustre User Group 2013. (2013)
Maeda, T.:
"Brief Introduction of HPC Usability Research Team"
In the 4th AICS International Symposium. (2013)

Posters/Flyers

Abe, T. and Maeda, T:
"Research on Program Verification Considering Various Memory Consistency Models"
The 13rd Dependable System Workshop (DSW2015). Poster. (2015) (in Japanese)
RIKEN AICS HPC Usability Research Team:
"HPC Usabiilty Research Team"
Exhibition of International Supercomputing Conference (ISC) High Performance. Poster. (2015)
Bryzgalov, P.:
"Eclipse PTP and TAU with K and FX10 Supercomputers"
Exhibition of International Supercomputing Conference (ISC) High Performance. Flyer (PDF). (2015)

Python ported to the K computer. Available on the K computer. Simply do ". /opt/aics/hpcu/env.sh" on the computing nodes of the K computer, then follow the documents of Python.
NumPy ported to the K computer. Available on the K computer. Simply do ". /opt/aics/hpcu/env.sh" on the computing nodes of the K computer, then follow the documents of NumPy
MPI4Py library ported to the K computer. Available on the K computer. Simply do ". /opt/aics/hpcu/env.sh" on the computing nodes of the K computer, then follow the documents of MPI4Py
MapReduce-MPI library ported to the K computer. Available on the K computer. Simply do ". /opt/aics/hpcu/env.sh" on the computing nodes of the K computer, then follow the documents of MapReduce-MPI
Eclipse PTP ported for the K computer (link).
TAU ported to the K computer. Available on the K computer.
Extrae ported to the K computer. Available on the K computer.
Scalasca ported to the K computer. Available on the K computer (Joint work with Programming Environment Research Team of AICS).
Python binding of EigenExa (joint work with Dr. Shimazaki of Computational Molecular Science Research Team of AICS. Partially feedbacked to the original source tree of EigenExa, developed by Large-scale Parallel Numerical Computing Technology Research Team)
Python binding of Rokko (Integrated Interface for Libraries of Eigenvalue Decomposition) (joint work with Dr. Sakashita and Prof. Todo of the University of Tokyo. Feedbacked to the original source tree of Rokko).
DockerIaaStool: Tools for creating a simple Infrastructure-as-a-Service system with Docker
QEMU on the K computer: CPU emulator for executing Intel binary executables on the K computer (implemented by extending the original QEMU emulator. In preparation for publication.)
K-scope with SSHConnect (joint work with Software Development team of AICS)
ABySS on the K computer: Parallel, paired-end sequence assembler (implemented by modifying the original ABySS so that it scales on the K computer. In preparation for publication.)